Semiconductor integrated circuits have great advantages in computer memory. The cost per bit of storage, and the speed of operation, provided by N-channel MOS random access memory (RAM) devices have resulted in their wide use in digital equipment, particularly minicomputers. One example of such a device, a 4096-bit RAM, is shown and described in U.S. Pat. No. 3,909,631, filed Aug. 2, 1973, by Norishisa Kitagawa, assigned to Texas Instruments Incorporated.
Typically, a semiconductor RAM accepts a multiple bit address from external circuitry, which address functions to select a specific cell (or cells) within the RAM for writing in data or reading out data. The address is generated by other parts of the system, separate from the RAM. Thus, a requirement placed on the circuitry of the RAM is that the timing and voltage levels (or logic levels) of the address signals to which it responds must be compatible with the remainder of the system.
Often, the voltage levels of the input address to a memory are low level bipolar voltage levels, such as TTL, rather than high voltage levels such as MOS; and low voltage input address signals create a design problem for the input address buffer. This is because such signals do not fully turn on MOS logic gates; and thus, are difficult to sense. Yet, the sensing of such signals must be performed both accurately and rapidly to enable the memory system to be reliable and fast.
In the past, input address buffers have been designed to operate with low voltage address signals. One example of an address buffer is shown in copending U.S. Patent Application Ser. No. 624,813, filed Oct. 22, 1975, by Redwine and Kitagawa, assigned to Texas Instruments; while this buffer circuit represented an improvement in speed, low power and noise level, there is a continuing need for improvement in these factors as the density of memories increases.
It is therefore an object of the invention to provide an improved circuit for detecting memory address signals.
It is another object of the invention to provide an input address buffer with relatively fast operating characteristics.
It is still another object of the invention to provide an input address buffer which accurately detects low voltage level input signals.